/**
 * @file     drv_adc.c
 * @author   Motor TEAM
 * @brief    This file provides all the driver functions for the ADC.
 *
 * @attention
 *
 * THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
 * CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
 * TIME. THEREFORE, METANERGY SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
 * CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
 * HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
 * CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
 *
 * <H2><CENTER>&COPY; COPYRIGHT METANERGY </CENTER></H2>
 */

/** Define to prevent recursive inclusion */
#define _DRV_ADC_C_

/** Files includes */
#include "myg0025_rcc.h"
#include "myg0025_misc.h"

#include "drv_adc.h"
/**
 * @addtogroup MY32_Hardware_Driver_Layer
 * @{
 */

/**
 * @addtogroup Drv_ADC
 * @{
 */

void Drv_Adc_Basic_Init(ADC_TypeDef *pAdc)
{
    /** Define the struct of ADC configuration */
    ADC_InitTypeDef  ADC_InitStructure;
    Queue_InitTypeDef Queue_InitStructure;
    
    ADC_StructInit(ADC,&ADC_InitStructure);

    ADC_DeInit(ADC);

    /** Enable the ADC1 clock */
    if (ADC == pAdc)
    {
        RCC_APB1PeriphClockCmd(RCC_APB1Periph_ADC, ENABLE);
    }
    else
    {
        return;
    }

////    ADC_ClockModeConfig(ADC, ADC_ClockMode_SynClkDiv2);
    RCC_ADCCLKConfig(RCC_ADCCLK_PCLK);

    /**
     * Initialize the ADC to 12bit
     * ADC clock 6 frequency division
     * Single period mode
     * ADC conversion is triggered by TIM1_CCR4
     * Data right aligned
     */
    ADC_Queue_StructInit(pAdc, &Queue_InitStructure);

    Queue_InitStructure.ADC_Queue = QUEUE_0;
    Queue_InitStructure.ADC_Queue_SWTrig = DISABLE;
    Queue_InitStructure.ADC_Queue_ExternalGpioFilter = DISABLE;
    Queue_InitStructure.ADC_Queue_CirculationMode = DISABLE;
    Queue_InitStructure.ADC_Queue_StepMode = DISABLE;
    
    Queue_InitStructure.ADC_Queue_Priority = PRIORITY_0;
    Queue_InitStructure.ADC_Queue_Mode = QUEUE_MODE_SH_SINGLE;
    Queue_InitStructure.ADC_Queue_Element = ELEMENT_0 | ELEMENT_1 | ELEMENT_2 | ELEMENT_3;
//    Queue_InitStructure.ADC_Queue_Mode = QUEUE_MODE_SH_DUAL;
//    Queue_InitStructure.ADC_Queue_Element = ELEMENT_0 | ELEMENT_1;
    Queue_InitStructure.ADC_Queue_Channel[QUEUE_1ST_CHL] = ADC_Channel_12;  //U current
    Queue_InitStructure.ADC_Queue_Channel[QUEUE_2ST_CHL] = ADC_Channel_11;  //V current
    Queue_InitStructure.ADC_Queue_Channel[QUEUE_3ST_CHL] = ADC_Channel_0;  //VBUS
    Queue_InitStructure.ADC_Queue_Channel[QUEUE_4ST_CHL] = ADC_Channel_9;  //VR
    Queue_InitStructure.ADC_Queue_Sample_Cycle = ADC_SampleTime_7_5Cycles;
    Queue_InitStructure.ADC_Test_Queue_BK = DISABLE;
    Queue_InitStructure.ADC_Queue_Replace = DISABLE;
    ADC_Queue_Init(ADC, &Queue_InitStructure);
    ADC_ExtTrigConfig(ADC, QUEUE_0, EXT_TIM1_CC4, EXT_TRIG_RISING);
    
    ADC_InitStructure.ADC_ClockDiv = ADC_ClockDiv_2;
    ADC_InitStructure.ADC_TrigDiv = ADC_TrigDiv_1;
    ADC_InitStructure.ADC_Sample_Hold = SH_SAMPLE_HOLD_5_Cycles;
    ADC_InitStructure.ADC_Chl_Hold = CHL_HOLD_1_5_Cycles;
    ADC_InitStructure.ADC_SH_Sample_Cycle = ADC_SAMPLE_CYCLE1_8_Cycles;
    ADC_InitStructure.ADC_EOC_SOC_DIS = EOC_SOC_DIS_1_5_Cycles;
    ADC_InitStructure.ADC_Power_Mode = ADC_HIGN_POWER_MODE;
    ADC_Init(ADC, &ADC_InitStructure);
    /** External triggering was enabled */
//    ADC_ExternalTrigConvCmd(pAdc, ENABLE);
}

void Drv_Adc_Channel_Init(ADC_TypeDef *pAdc, uint32_t s32SampleTime)
{

}


/**
  * @}
*/

/**
  * @}
*/
